As is known in the art, DACs have been used in a wide variety of applications to convert an N-bit digital word into a corresponding analog signal. One such DAC includes a string of 2N resistors having substantially the same resistance serially connected across a reference voltage. Thus, the resistor string divides the reference voltage among the resistors in the string. A switching network is provided for coupling the voltage at one of the resistors to an output to produce the converted voltage. While such a DAC is suitable for applications where N is relatively small, when N is large, for example, where N is in the order of twelve, 4,096 resistors, 4,096 switches, and 4,096 control lines are required thereby resulting in a relatively large number of elements to be fabricated on an integrated circuit chip.
One technique suggested to reduce the number of elements is to use a segmented converter. In a segmented converter, a first stage uses a resistor string for converting a group of higher order bits of the N-bit digital word and a second stage decodes the remaining, lower order bits. A non-linear converter of that general type is shown in an article by Gryzbowski et al., entitled “Non-liner Functions from D/A Converters”, Electronic Engineering 1971, pgs. 48–51. The converter disclosed in that article is designed for operation with relay switching and is not readily adapted to modern semiconductor technology. Another segmented converter is described in U.S. Pat. No. 3,997,892, issued December 1976, inventor Susset. The segmented converter described in U.S. Pat. No. 4,543,560 includes a resistor string for both the first and second stages with buffer amplifiers between the stages to prevent the second stage resistor string from loading the first resistor string.
Another type of segmented DAC is described in U.S. Pat. No. 5,495,245, issued Feb. 27, 1996, inventor James J. Ashe, assigned to the same assignee as the present invention. The DAC described therein includes a pair of first stage resistor strings coupled to a second resistor string through a first switching network. A pair of reference voltages are coupled to the pair of resistor strings. The first switching network operates such that a voltage produced at a selected one of the resistors in one of the pair of first stage resistor strings and a voltage produced at a selected one of the resistors in the other one of the pair of first resistor strings are coupled across the second stage resistor string. A second switching network couples an output at a selected one of the resistors in the second resistor string to an output of the DAC. Buffer amplifiers are not included between the pair of first stage resistor strings and the second stage resistor string. Two arrangements are described. In one arrangement, the first switching network responds to the Most Significant Bits (MSBs) and the second switching network responds to the Least Significant Bits (LSBs). In the other arrangement, the first switching network responds to the LSBs and the second switching network responds to the MSBs. In former arrangement, each resistor in the pair of resistor strings has a value 2N*R, where R is the resistance of each of the 2N/2 resistors in the second resistor string. In the latter arrangement, each resistor in the second resistor string has a value 2N/2*R, where R is the resistance of each resistor in the pair of first resistor strings. In both arrangements, the entire current passing between the pair of reference voltages passes through the resistors. Therefore, while such arrangements are useful in many applications the relatively high number of resistors which are required in both the first and second pairs of resistor strings thereby requiring relative large chip surface area for their fabrication.
Another problem with these type of DACs is that low ‘on’ impedance requires large switches that have large unwanted parasitic capacitance due to the relatively large area of the switches. This capacitance results in slowing down the switching transient operation of the converter and limits higher speed performance. Minimum sized switches are therefore desirable to minimise the capacitance. A further problem with large, low ‘on’ impedance switches is that they have proportionally higher device leakage currents. Diode leakage and MOS ‘off leakage’ are an unwanted error component in string DAC's. The leakage components are also highly temperature dependent and these leakage currents can limit the maximum operating range of an Integrated Circuit (IC). Minimum sized switches are therefore desirable to minimise device leakage effects.
A further type of DAC is described in U.S. Pat. No. 5,969,657 issued Feb. 19, 1999, inventor Dennis Dempsey et al, assigned to the same assignee as the present invention and incorporated herein by reference. Referring to prior art FIGS. 1 and 2, a DAC 10 is shown to adapted to convert an N bit, here N=4, digital word, I4 I3 I2 I1, (where bit I1 is the least significant bit (LSB) and I4 is the most significant bit (MSB)) into a corresponding analog signal, Vo, at output terminal 11. The DAC 10 includes a pair of resistor strings 12, 14. Resistor string 12 is adapted for coupling across a voltage supply 15. The voltage supply 15 produces a voltage, +V, at terminal 16 relative to ground potential at terminal 18. The first resistor string has a plurality of, here 2N/2, (i.e., 4) resistors Ra1–Ra4, serially connected between terminals 16 and 18, as shown. The resistance of each one of the resistors Ra1–Ra4 is here R1 ohms. It is noted that resistors Ra1, Ra2, Ra3 and Ra4 have: resistor Ra1 terminals T0, T1; resistor Ra2 terminal T1, T2; resistor Ra3 terminals T2 and T3; and, resistor Ra4 terminals T3 and T4, respectively, as shown. Resistor Ra4 terminal T4 is connected to terminal 16 and resistor Ra1 terminal T0 is connected to input terminal 18, as shown. The resistors Ra1–Ra4 in the resistor string 12 produce voltages at the terminals T1–T3 in response to current fed thereto from the voltage supply 15.
The second resistor string 14 has a plurality of, only 2N/2−1, here three resistors Rb1, Rb2, and Rb3 of substantially equal resistance, have a resistance of R2 ohms, serially coupled between a pair of second resistor string 14 input terminals 26, 28, as shown. It is noted that 2N/2−1 is an odd integer. Resistors Rb1, Rb2 and Rb3 have: resistor Rb1 terminals Q1, Q2, resistor Rb2 has resistor terminals Q2, Q3, and resistor Rb3 has resistor terminals Q3, Q4, respectively, as shown. Terminal Q1 is connected to input terminal 28 and terminal Q4 is connected to input terminal 26.
The DAC disclosed by U.S. Pat. No. 5,969,657 integrates the MSB switch impedance into the transfer function such that the MSB switch impedance causes a step in the transfer function of one LSB when the LSB DAC switches between neighbouring MSB resistors. The impedance of the MSB switches is proportional to the DAC resistors, thereby requiring a larger area for each switch for applications which require reasonably low impedance switches. A requirement for low impedance switches can increase the IC surface area and cost of a circuit, which is undesirable and restricts the design of the DAC. Additionally a problem with large low impedance switches is that due to the larger surface area the self capacitance of the switch increases which slows down the speed of the DAC and diode leakage which sets a lower power operation limit. Switch capacitance is also a particular problem for high speed DAC's which are implemented using MOS design or other similar switch design techniques.
There is therefore a need to provide a Digital to Analog Converter which saves on chip surface area, reduces the number of resistors and implementation cost, reduces the self capacitance and the device leakage currents of the circuit elements. A further need is to increase the DAC transition speed and improve the overall performance of the converter. Another need in the field of Digital to Analog Converters is to increase the accuracy of a dual string digital to analog converter by reducing the number of device leakage components. A further need is to increase the operation temperature range for the switching devices in a switched dual string digital to analog converter.